This invention relates to an improvement for a a parallel/serial converter which converts parallel signal sequence into a serial signal sequence.
A parallel/serial converter of this type has been used for an interface which converts parallel data from a computer or a communication system to serial data and a multiplexer which multiplexes a plurality of data sequences from plural channels.
A prior art parallel/serial converter comprises a parallel input/serial output shift register and a holding register connected to the parallel input side of the shift register as a buffer store means. (See, for example, pages 4-9 of "Technical Aspects of Data Communication" (in Japanese) published by CQ Publishing Company, on Apr. 20, 1980). The holding register loads and stores n-bit (n is an integer) parallel input digital data with a load input, and then the shift register receives the stored data in parallel from the holding register to shift n-bit serial signal on a bit by bit basis with a shift clock signal which has a higher rate than the input digital data. When the shift register has shifted out the n-bit serial data, it receives the next n-bit parallel outputs from the holding register and then converts them to serial data. If the signal rate of the parallel input signal sequence increases, the store means should receive and store each of the parallel input signals at a rate proportionally higher. Therefore, the prior art parallel/serial converter can not operate at the signal rate beyond the capacity of the operational frequency of the holding register and the latch circuit.